In non-isolated DC-DC converters such as the buck converter, an optimal transient load condition response may be achieved by proper timing of the high-side and low-side transistors so as to balance the charge on the output capacitor of the converter. Such an approach achieves the minimum undershoot possible for a given design. In isolated topologies such as full-bridges and half-bridges where the primary side of the converter is coupled to the secondary side by a transformer, transformer core saturation prevents direct application of the non-isolated approach mentioned above. With linear control loops, transformer core saturation during transient load conditions is conventionally avoided by oversizing the transformer core and assuming a maximum duty cycle may be applied at the minimum input voltage. Alternatively, the maximum duty cycle is limited as a function of the input voltage which degrades transient response. In either case, a more optimal response that avoids transformer core saturation in isolated DC-DC converters without increasing the size or cost of the converter is desired.